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AD7648 : slowest fclk and affect

Question asked by ysuzuki on Jun 8, 2017
Latest reply on Jun 16, 2017 by SeanWilson

Hello,

 

I have a question about AD7468 SAR ADC.
The AD7648 has a specification about fclk as followings. (tabel-4 of the datasheet)

 

Parameter     Limit at TMIN,TMAX     Unit        Description
   fSCLK             3.4           MHz max         Mark/space ratio for the SCLK input is 40/60 to 60/40.
                           10            kHz min         1.6 V ≤ VDD ≤ 3 V; minimum fSCLK at which specifications are guaranteed.
                           20            kHz min         VDD = 3.3 V; minimum fSCLK at which specifications are guaranteed.
                         150            kHz min         VDD = 3.6 V; minimum fSCLK at which specifications are guaranteed.

 

It means that fclk has a limitation of lowest speed, affected by VDD.

 

Q1. Which performance will be affected if the fclk more slower than this ?
    SNR ?   INL ?   DNL ?

 

Q2. Would you tell the lowest frequency of fclk when the VDD is 3.4V ?

 


Best regards,
ysuzuki

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