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TDD Tristate control for P0_D / P1_D

Question asked by James.Speros on Jun 6, 2017
Latest reply on Jun 12, 2017 by sripad

I am using the AD9361/AD9364 in TDD mode in conjunction with an FPGA as the BBP.  The data interface is set up as Dual Port Half Duplex Mode (CMOS).  I have been using TXNRX directly to control the tristate buffers for the bidirectional P0_D and P1_D signals.  The TXNRX signal retains its state after a burst, so when an RX finishes, TXNRX stays low and I expect the transceiver to continue driving the Px_D buses.  Then I found this in the reference manual:

The direction of data transfer is determined by the TXNRX signal. When this signal is low and the AD9361 is in the FDD state or the Rx state, the ENSM configures the bus in the receive direction (data transferred from AD9361 to BBP). All other states result in the bus being set to high impedance.

The implication is that at some point after the RX completes, the transceiver will stop driving the Px_D buses.  In my current system, they will remain undriven by both the transceiver and the BBP until the next burst.  This seems to violate this requirement from the reference manual:

The P0_D[11:0] and P1_D[11:0] bus signals are usually actively driven by the BBP or by the AD9361. During any idle periods, the data bus values are ignored by both components. Both ports, however, must have valid logic levels even if they are unused.

So here are my questions:

  • What is Analog Devices' recommendation for control of the tristate buffers?
  • Am I supposed to use RX_FRAME to know when the transceiver has stopped driving the bus and then revert to the BBP driving it?
  • For how much time is it acceptable to leave the buses completely undriven (i.e. turnaround)?