AnsweredAssumed Answered

adv212 HIPI encode, get many many DREQ0 asserts but no DREQ1 assert

Question asked by wangyubin on Jun 6, 2017
Latest reply on Jun 14, 2017 by DaveD

hello everybody,

I am using adv212 to encode a picture in HIPI mode, MCLK is 50MHz. I write parameters just as franky did, which is on "", then I read "FF82" from SWFLAG. After I configure DMA0 and DMA1, I get the first DREQ0 assert. And after I write 0x00000400 to EIRQFLG, I start to write YCbYcr 32 bits to HDATA, the burst length is 128, then I wait for another DREQ0 assert, if DREQ0 asserts, I write another 128 YCbYcr 32 bits, and so on. Using Chipscope in ISE, I can see many DREQ0 asserts, it will not stop. But I can not see DREQ1 assert.

1. I check the sc0~sc3 pin on PCB, it is 0x7, and I really doubt that I have not written data into pixel fifo correctly, the folllwing is my DMA timing, please check the DMA0 writing if it is right or not(MCLK=50M, DMA0 writing clk=25M, maybe I need to wire sc0~sc3 to FPGA pin, so I can look into them in ChipScope):

DMA timing

2. I get to know that there was a guy meeting the same problem, but it turned out that it was voltage ripple, and my 1.5v is pretty ok.

3. The following is my Encode initialization, just as the one on the website I mentioned above, which is successfully used by franky in encode mode. So I really do not know where I am wrong except Point 1.
ENCODE initializiton:
1. Write 0x00000008 to the PLL_HI register, 0x00000084 to the PLL_LO register
2. Wait for 1ms
3. Write 0x0000008A to the BOOT register
4. Write 0x0000000A to BUSMODE
5. Write 0x0000000A to MMODE
6. Write 0x00050000 to IADDR
7. Load <encode_2_13_0.sea>
8. Write 0x0000008D to the BOOT register
9. Write 0x0000000A to BUSMODE
10.Write 0x0000000A to MMODE
(2) Pre-initialization Routine for ADV202
1. Write 0x00057F00 to IADDR
2. Write 0x04000503 to IDATA
3. Write 0x01000000 to IDATA
4. Write 0x02000500 to IDATA
   Write 0x00000002 to IDATA
5. Write 0xFFFF0400 to IADDR (0xb); select PMODE register
   Write 0x00150000 to IDATA (0xc); 8-bit YCbYCr
   Write 0xFFFF040C to IADDR (0xb); XTOT
   Write 0x05000000 to IDATA (0xc); 1280
   Write 0xFFFF0410 to IADDR (0xb); YTOT
   Write 0x01E00000 to IDATA (0xc); 480
   Write 0xFFFF044C to IADDR (0xb); VMODE
   Write 0x00120000 to IDATA (0xc), Host mode enabled for HIPI encode mode
(3) Initialization Routine for ADV202
1. Write to 0x0400 to EIRQIE
2. Wait for IRQ to be asserted
3. Read SWFLAG to ensure the program has correctly initialized (i had read the data->0xFF82)
(4) configure DMA channel 0 for pixel input
1. Write 0xFFFF1408 to IADDR
2. Write 0x01100000 to IDATA
3. Write 0xFFFF1408 to IADDR
4. Write 0x01110000 to IDATA
(5) configure DMA channel 1 for compressed data output
1. Write 0xFFFF140C to IADDR
2. Write 0x01120000 to IDATA
3. Write 0xFFFF140C to IADDR
4. Write 0x01130000 to IDATA
(6) Start program for ADV202
Write 0x0400 to EIRQFLG on the ADV202 to clear the software interrupt [SWIRQ0]