We are using HDMI Tx(AD9889B) and HDMI Rx(ADV7441A) in our setup.
In one board(BOARD1) FPGA drives digital RGB, VSYNC, HSYNC, DE, and PCLK to HDMI Tx.
In the other board(BOARD2) the HDMI Rx digitizes data from HDMI channel and outputs digital RGB, VSYNC, HSYNC, DE, and PCLK to FPGA.
The BOARD1 HDMI Tx output is loopbacked to BOARD2 HDMI Rx input.
We have done HDMI Tx configuration as per attached file(HDMI_Tx_configuration.c) for 720x480@60fps, and HDMI Rx configuration as per attached file(HDMI_Rx_configuration.c) for 720x480@60fps.
We are sending Red-Green-Blue bars from BOARD1 FPGA with timing as per EIA/CEA-861-B.
(VSYNCFP= 9,VSYNCPW= 6, VSYNCBP= 30, HSYNCFP= 16,HSYNCPW= 62, HSYNCBP= 60)
Red-Green-Blue bar is received in the BOARD2 FPGA with single pixel data corruption on every alternate line.
The first pixel of every alternate line during active video from HDMI Rx to FPGA is not the expected value.
We found that Timing details read from HDMI Rx is not matching with the HDMI Tx timing.
HDMI Rx detected timing is HSYNCPW=62; HSYNCBP=59; HSYNCFP=17; VSYNCPW=6; VSYNCBP=30; VSYNCFP=9.
Note that if we connect the output of HDMI Tx to HD monitor the display is perfectly fine.
Does anybody have an idea what may be missing or wrong. Please help us to resolve the issue.
Thanks in advance.