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HDL reference design about AD9361 based on Xilinx FPGA platfrom

Question asked by YosenBian on Jun 1, 2017
Latest reply on Oct 20, 2017 by YosenBian

Hi ,

    I have already build up the HDL reference design based on Xilinx FPGA Zedboard, following the methods on the webpage below.

https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/reference_hdl

https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/software/no-os-setup

 

 I do not set up the Linux OS , and I just use the no-os software on SDK.

 

My Vivado tool version is 2014.4. So I use the the hdl package "hdl-hdl_2015_r1" which requires Vivado2014.4.1.

After I package all the IPs needed in "./hdl-hdl_2015_r1/library", I source the "system_project.tcl" in "./hdl-hdl_2015_r1.projects/fmcomms2/zed." And then Vivado builds up block design ,Synthesize, implementation, Generate bitstream automatically. And there are no timing and other errors information.

Then I follow the flows in the second webpage.

 And then I program the FPGA and run the application. I analyze the spectrum on frequency analyzer. It's OK.

when I setup the hardware as shown below. I supposed to receive a 1Mhz sine ware in Chipscope.

But I just receive the ware shown below.

 

 

siganl is the low 12 bit of the bus whih is captured by ila. and i have already change the radix into signed demical and display as analog signal. so the wave should be cntinuous.

 

I DO NOT MODIFY THE HDL.

I just insert one line in “main.c”.

#define XILINX_PLATFORM

I do not change any configuration information in the no-OS software reference design.

Do I make any mistakes??

And I have tried the AD9361 test mode. The result is the same. I think something wrong with the rx channel. But I don’t know what problem is.

How could I fix this problem.

 

Thanks.

 

 

 

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