The ADRF6820 datasheet list the typical integrated phase noise as 0.6 deg RMS.
quote: "1 kHz to 40 MHz integration bandwidth, PFD = 38.4 MHz, fREF = 153.6 MHz, divide by 4, charge pump = 250 µA, loop bandwidth = 20 kHz, antibacklash delay = 0 ns, charge pump bleed current = 46.8 µA down, LO frequency = 1562.5 MHz"
Putting the same design params into ADIsimPLL (4.20.02) I get 0.29 deg RMS ignoring reference noise (and similiar using a model of my intended reference which has negligible impact.) Where did the measurement on the datasheet come from... there are no (useful) plots - do you have any? Presumably the measurement wasn't taken with an awful reference / noisy power rails... so which is closer to the truth. Even turning on dither (surely you wouldn't have for this measurement?) I only get 0.43deg rms simulated. [Sorry can't post report of simulation as it is on another machine]
I did my detailed design work using ADIsimPLL and was happy with PN performance but am now worried as 0.6deg won't meet my specifications so may need additional external LO... so can I trust the simulator assuming I take care of my reference, psu noise etc.