I'm currently working on implementing a new DSP module in my HDL code, and I'm trying to send an array of integers to the FPGA. It looks like libiio supports this using iio_channel_attr_write(), but I can't find an example of how this is implemented on the driver side.
I have my own iio device with my own driver that is connected to my custom HDL module, and I can write to an AXI interface, but I only know how to write single 32 bit numbers. Should I just loop through each integer and write them one at a time? I feel like there is a better way (Such as a AXI Stream interface), but I don't have a good example to go off of.
Sorry if this question is a bit vague, I really just need a starting place and I'll be off and cooking.