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AD9371 Calculate Digital clocks

Question asked by Abhisheknaik on Jun 1, 2017
Latest reply on Jun 8, 2017 by gverma

Hello everyone,

                 We have purchased xilinx zc706 and adrv9371 evk board. In AD9371 Evaluaton software whenever we change device clock(configuration tab) HS_DIGCLK(Rx summary) is also changing. Following are table of device clk v/s HS dig clk.

Device Clk(MHz)HS Dig clk(MHz)




            After going through datastructure created by AD9371 TES. We came across following structure.

device clk = 122.88MHz
static mykonosDigClocks_t mykonosClocks =
122880, /* CLKPLL and device reference clock frequency in kHz*/
9830400, /* CLKPLL VCO frequency in kHz*/
VCODIV_2, /* CLKPLL VCO divider*/
4 /* CLKPLL high speed clock divider*/


We are facing problem in relating above parameters. From our observation from TES and from figure 27 in ug-992, we came to know that HS dig clk depends on dev clk, vco freq, vco divider and hs clk divider.


Is there any formula to calculate HS Digital Clock?


Where can I get explanation for MYKONOS_calculateDigitalClocks() API? We went through ug992 doc, But we didn't find explanation for that.


Thanks and Regards,

Abhishek Naik.