Dear Fellows and Staff;
Probably my theoretical and practical knowledge about PLL design is not enough, but I need to understand following things, so please guide me on being able to generate 1087, 1090 and 1093 MHz signals with ADF4106.
1) What is the correct PFD frequency to be set? I believe it has to be a value which can divide all the RF output frequencies (therefore it can be maximum 1 MHz) I want to generate. And from the ADIsimPLL, the bigger the PFD frequency value provides a lower phase noise level. Would you please confirm that?
2) As I don't have any locking duration concern, I plan to use the narrowest loop filter bandwidth to decrease the overall phase noise and spur levels. I plan to use an active loop filter (with THS4032MDGNREP for Vbias = 5V). I believe the bandwidth is not related with the PLL's (and therefore PFD's) soft settings at all, would you please confirm that?
3) This part has a 3-wire SPI protocol (CLK, DATA, LE). I am used to 4-wire SPI protocol (CLK, MOSI, MISO, CS). On page 15 of UG-159 datasheet, which is an Evaluation Board User Guide, there is a kind of mapping, but I am not convinced. ADF4106_CLK is connected to SPI_CLK and ADF4106_DATA is connected to SPI_MOSI as I expected. And ADF4106_MUXOUT is connected to SPI_MISO, however the ADF4106 datasheet gives an impression that it is not a serial output but a discrete line. If it is truly a serial MISO, then what is the register map of the output (master-in-slave-output)? And finally, what is mapped in ADF4106 to Chip Select (CS) of 4-wire SPI? It looks like LE is a kind of CS, but I couldn't be sure about it. The thing is, I will use CS in my design for two PLLs (with ADF4106). Therefore, CS:1 should enable only LO#1, CS:0 should enable only LO#2, is it possible?
4) It seems (from ADIsimPLL) that the reference input frequency is not so effective as its (crystal's) phase noise is already much lower than overall phase noise, would you please confirm that?
Thank you in advance.