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DEV_CLK

Question asked by jyothibasu.dasari@mitel.com on May 31, 2017
Latest reply on Jun 13, 2017 by sripad

I am designing the transiver for 50MHz, and want use the AD9371 synthsis bandwidth of 250MHz.

if i provide a DEV_CLK of 122.88MHz clock to the AD9371, and my Input datarate is 307.3MSPS. is it possible to generat the ADC/DAC Digital clocks as 307.2MHz and 153.6MHz??

 

I din't find a relation between DEV_CLK and "ADC/DAC digital clock generator" in User guide "992".

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