Hi guys,

We are using many AD9218BSTZ-105 chips, which are used on ADC daughter boards. Now, we are testing those ADC daughter boards performances. One of the important specification is slope. Our question about slope is how to calculate (how to test it?) ADC's slope?

We are asking this qauestion becuase we tested it by input different DC values to ADC. For example: Input 0mV, 100mV, 200mV, 300mV, 400mV,500mV, 600mV,700mV,800mV,900mV and 1000mV into ADC channels respectively and get the sampling value. We collected 1000 samples at each constant DC value. Then we calculate this ADC's channel's slope according these collected sampling values.

We don't know if our method is correct or not? And how ADI calculate your ADC devices slope? We found that different ADC chips have different slopes. For example, sometimes is 0.97, sometimes 0.92, and sometime about 0.95, and so on. Is this ok when getting those slope ratio vary?

The input common mode range of the AD4930 is 0.8V-1.1V. The common mode voltage from the AD9633 is 0.9 which is within the range of the AD4930. The AD4930 can DC couple into the AD9633. Here is an example schematic: