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AD9680 Config Issues

Question asked by kiranvg@gmail.com on May 29, 2017
Latest reply on Jun 8, 2017 by kiranvg@gmail.com

Hi,

I am using AD9680BCPZ_1000 in my application. I am facing some configuration issues in bringing up the ADC. My ADC setting requirements are as below.

ADC Clock: 640MHz, LVDS
Sysref: 20MHz continuous, LVDS
Analog inputs: Differential 2MHz sine wave coming out of AD9152 DAC (for testing).
Analog input amplitude: Around 600mVp-p
SYNCINB: LVDS coming from FPGA
JESD Requirement:
L=4,
M=2
F=1
Lane rate: >6.25Gbps and <12.5Gbps
Don't want DDC and scrambling to be enabled
When I check the response from JESD204B receiver IP core on FPGA, it says ILAS is passed. But afterwards I am not getting any output in JESD lanes corresponding to the analog input.
I have attached the ADC configuration I am using and also the ADC register readback data. Request you to review the ADC configuration and let me know where I am going wrong. Kindly let me know if you need any more information.

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