Hi. I'm using an AD9914 as part of an AC offset cancellation scheme. For this purpose a low frequency (50MHz) reference is driving REF_CLK, multiplied x50 and divided /50 to create an amplitude/phase variable signal.

The problem is that when I combine the offset and the replica, the output signal power "jitters". I went through the datasheet and I'm wondering if this is a result of rounding error in the profile MOD2 frequency divider.

I noticed that if I use a 2^x multiplication/division ratio (e.g CLK_REF=39, MUL=64, SYS_CLK=2496) and then divide /64, I don't experience the erroneous behavior.

Am I correct? If so, is there a way to create an arbitrary output frequency which is locked to REF_CLK?

Thanks ahead.

Matan

The cause of the jitter is a result of the resolution of the DDS phase accumulator, which is 32 bits. With a 1/50 ratio for fout/fs, the required frequency tuning word is FTW=85,899,345.92 (note the fractional part: 0.92). Fractional tuning words are not allowed as the tuning word must be an integer by definition. The closest integer is 35,899,346, which yields a DDS output frequency of: 50.00000004656612873077392578125 MHz (not 50 MHz as desired). What you are seeing as output jitter is the resulting beat frequency of ~0.05 Hz.

As you have pointed out, the problem disappears when the fout/fs ratio is a power of two. The reason is the resulting tuning word has no fractional part -- it's a precise integer. The result is a perfect match between the desired and actual DDS output frequencies. You will need to maintain this 1/(2^x) relationship in order to get an exact match between the REFCLK signal and the DDS output frequency.