I'd like to generate a programmable clock input into the AD9780/81/83 DAC using an LVDS clock source from my FPGA. I noticed that the DAC sampling clock inputs (CLKP/N) have some special requirements and I wanted to share a possible solution with Engineerzone.
I'm using an LVDS-to-LVPECL buffer (part number MAX9377) to translate my source clock signal to a standard LVPECL differential signal. Then, instead of the (VCC-2V) termination for a standard PECL transmission line, I'm using a simple resistor divider as described in the datasheet to generate a 400mV common mode voltage. I've attached my circuit diagram to this post. Can anybody comment on the suitability of this circuit? Will it work?