In shutdown mode, what is the state of the Q,~Q outputs? Are these tri-stated (high impedance?)
This information seems to be missing from the data sheet.
I double checked this on the bench. The Q and Qbar outputs are indeed active when the part is disabled. The one thing that is different from above is the status of Q and Qbar after an ENBL cycle. On the bench, I noticed that the part does not correctly remember the status of Q and Qbar after an ENBL high-to-low-to-high cycle. So from the perspective of Q and Qbar, an ENBL cycle is the same as a power up cycle.
Got this back from the designer. I will double check this on the bench.
In sleep mode (enable low) , outputs Q and Qbar should remain as active, static-cmos driven, low-impedance outputs.
The sequence of gates in the PA protect chain is
latch -> 3-to-5 V level converter -> static cmos pad driver
The 3-to-5V level converter is gated by ENABLE to insure it does not float at startup.
Therefore, with enable low, the state of the outputs should be Q=LO, and QBAR=High.
*Note , depending on the supply ramp timing and enable timing, the part may or may not come up in the
state Q=0 once ENABLE is brought high [we tried do make this deterministic, but could not quite get
there over process variation]. A user - reset is required to reach a known state.
** If the part was previously brought up and ENABLE subsequently brought LO, then I believe
the part will come up in a known state (Q=LO) when ENABLE is brought HI a second time (provided
the signal level is below that on VTHRESH)
Thanks for the information. I had hoped for tristate, but never mind.
Retrieving data ...