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Question asked by hpkamen on May 28, 2017
Latest reply on May 28, 2017 by UmeshJ

Dear Sir/Madam,


With the monolithic AD9690 to acquire data to the FPGA,  without delay requirement, so I want to configure the AD9690 in JESD204B sublcass 0 mode. But under this mode,  how to deal with the AD9690 SYSREF ± input pin?  And what others we need pay attention to for the AD9690 working in subclass 0 mode?