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Advice on using my hw baseband on fmcomms4?

Question asked by MTYM on May 26, 2017
Latest reply on May 29, 2017 by rejeesh

   I have built the reference design, booted Linux on the design successfully; and also booted the No_OS firmware as well, although I had to make some changes to get everything to work. (using ZC706 board and Vivado 2015.4.2 as that is what seemed to be required by the reference).  This is a very nice system!

   Now I would like to use my baseband verilog to receive and transmit the data, instead of the supplied reference code; and to do so I have built an interface to the axi_ad9361_dev_if.v verilog, and arranged that I present the dac_data in the format that the axi_ad9361_dev_if expects; and accept the data it provides.  My baseband has an axis interface to a MAC for this protocol; and I will run that on the ARM9 CPU.

   I plan to leave the spi bus interface to the reference board unchanged, and use the routines from the adi reference firmware to set up the radio for transmit and receive.

   The reference design includes an axi_ad9361_dac_dma module and a axi_ad9361_adc_dma module and associated logic (fifos, pack and unpack), which I would delete.

   The reference design includes support for HDMI screen which I plan to delete.

   I have copied the gpio bus infrastructure from system_top wrapper, and include that in my design.

 

   As I proceed on this effort, I notice that while most of the firmware operates by using spi bus reads and writes, or directly reading/writing the gpios (all which should continue to work fine on my build), some operations read and write commands to registers on the axi_bus  ( as an example dss_update calls dds_set_frequency, which calls dac_stop. which writes to the DAC_REG_CTRL address).  This *looks* like is is perhaps just controlling the axi_ad9361_dac_dma module; but before I go further I figured I would ask:

 

   Is it even feasible to do what I am attempting here?  Or are there some tight requirements between features

   (a) the radio chip,

   (b) the data path that is in the axi_ad9361_[dac|adc]_dma modules, and

   (c) the firmware

that implement key features like AGC?  As an example, does fast attack AGC depend on the fw seeing the data stream so it can change the values for attenuation on the fly?  Or is fast AGC done completely in the radio chip?

 

   Is my strategy the best one, or is there some other targeted reference design that has already done much of what I am doing, and hence I could start from there?

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