We are experiencing an issue that happens quite infrequently (once every few hundred to maybe a thousand power ON cycles) but when it does - the DCO clock coming from the AD9648 is missing (stuck HIGH). The input clock is fed by a Silabs programmable PLL Si5335A (125MHz LVDS) and confirmed within specs, while the DCO output clock drives an FPGA PLL (125MHz single-ended). I've attached a snippet of the schematic which is straightforward. I found that there were a few other users reporting the same issue, but after the initial description all discussions became private (via email). I find this a little suspicious - is there a known issue with this part that must only be discussed privately? Can this not be made available for all other users to read?