I'm experiencing a problem in using AD9361 .
Starting from reference design (2015_R2 linux and hdl branch, Zynq board)...I inserted a custom VHDL modulator.
My example is based on 40Mhz Sample Rate and 5 Mhz bandwith QPSK modulation.
The sample rate (40 Mhz) and bandwitdh (5Mhz) are set through the example application that set data clock to 160 Mhz in order to have the 2 I/Q channels to 40 Mhz each.
Both the TXs are enabled but only one is fed by the modulated stream, the other ones is fed by zeros.
The simulation up to the LVDS DDR output shows a correct output bandwith but on the spectrum analyzer I see a bandwith more or less 4 times higher than expexted.
I also tried to configure the AD9361 tx chain with the file generated with the Matlab app (attached) and also tried to simulate with the Simulink Model with a 40 Mhz source and a 5 Mhz QPSK modulator which shows a correct bandwidth.
As a last test i used the same data of the Simulink Model to feed the DMA buffer (long enough to see an output burst) bypassing the modulator but i still doesn't see a correct bandwidth.
Does anyone have any idea about this behaviour?