I am struggling to understand how clocks are setup in this example.
From the manual (Preliminary Technical Data, SHARC+ Dual Core
DSP with ARM Cortex-A5, ADSP-SC570/571/572/573/ADSP-21571/21573):
TM0_ACLK5 TIMER0 Alternate Clock 5 Not Applicable DAI0_PIN03
The Alternate Clock 5 output is on DAI0_PIN03. DAI0_PIN03 is routed to the external input of the PCG.
The PCG is set up in function PcgInit, dividing the input with 0x8 for clock and 0x200 for frame sync.
I have two questions:
- The readme says that frame rate is 96 kHz to AD1962a, but the code says 48 kHz. Is there a confusion because the channel is in stereo?
- How is TIMER0 Alternate Clock 5 initialized? There is no code in the example. Is there a default configuration set in hardware? I cannot find the documentation.