The datasheet states sample rates between 300 ksps and 1200 ksps are possible. Presumably this requires a clock input at 48 X the sample rate and the PLL bypassed?. The internal PLL can only be used for sample rates of 115200 / N / 48 ksps ? All frequency responses scale with sample frequency? Is operation below 300 ksps possible ?

Many thanks

Chris

Hi Chris,

The ADAR7251 is sigma delta ADC which oversamples the signal and then decimates it down to the required sample rate at the output. So once the PLL is set for the correct clock rate, there are different decimation rates possible. Depending on the decimation rate the other sample rates can be possible. See register 0x0140. The possible rates are from 1.8MSPS/1.2MSPS/900KSPS/600KSPS/450KSPS/300KSPS.

Yes, the digital filter frequency response will scale with sample rate selected.

It seems you are looking for 300K which should be possible with Reg 0x0140 set to 0x0007.

Regards

Rajeev