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AD9625 Eye Diagram

Question asked by checkandmate on May 23, 2017
Latest reply on Jun 8, 2017 by rejeesh



I have 8 JESD204b lanes coming from an AD9625 ADC running at 6.25Gbps into 8 GTX ports on a Xilinx Zynq FPGA. I want to view the RX eye diagram. I am attempting to use IBERT in Vivado with no success. I manage to lock my PLL's and get the line rate to successfully read a line rate of 6.25Gbps. However, when I run a scan I get a completely red eye diagram:


All Links Up but No Eye


There is an ADI article that talks about JESD eye scan (link) that uses the IBERT core from its description. However the software it provides runs on eval boards that I do not want to use as I want to see the eye in my real system.


Is there a a parameter that I may not be setting correctly? Could I somehow use the software from the article without the eval board?