I am experiencing some problems while trying to get SPI working on an ADSP21992. I know the ADSP21992 is a senior citicen but I have no other choice. The setup is rather simple (master/no dma).
Now my problem:
I can't see the RXS bit change to indicate the end of transmission while sending out data (master), as suggested in the hardware reference.
Basically I am doing the following:
1) Setup SPI
1.1) Set SPIFLG register to disable all slaves by setting the corresponding bits in the high and low byte.
1.2) Setup the SPICTL register
TIMOD = 01
SZ = 0
GM = 1
PSSE = 0
EMISO = 0
SIZE = 0
LSBF = 0
CPHA = 1
CPOL = 1
MSTR = 1
WOM = 1
SPE = 1
1.3) Set the SPIBAUD register 0x50 (500kHz) @160Mhz
1.4) Setup the SPIFLG register to enable one slave by setting the corresponding bits in the high and low byte.
2.1) Wait for TXS low before writing to TDBR
2.2) Clear all error bits in SPIST
2.3) Write 1 byte to TDBR
2.4) Wait for RXS high
2.5) Read RDBR
3) Disable slave
3.1) Set SPIFLG register to disable all slaves by setting the corresponding bits in the high and low byte.
Waiting for RXS high doesn't seem to work and when I output the status register bits to FIO ports I can't see any change in the signal there either. RXS is always high.
Waiting for SPIF does work and the output on the FIO shows that too. However when waiting for SPIF I am getting the RBSY error flag set on each transmission and I can't see any reason why. Is this normal?
Also I need 2 nops between 2.3) and 2.4) in order to let SPIF go low before polling which is not a desaster in itself but was rather hard to guess.
Any idea what I am getting wrong about the RXS bit and/or if there is any harm in using SPIF.
I'd be glad if somebody could provide me with some help.