We have some doubts about our block design – please see attachment with block diagram. May I kindly ask you to check if my intentions are correct?
First of all I have read threads with similar questions but many of them are only about single-board systems (HMC7044/43 combination etc). I have also read http://www.analog.com/media/en/technical-documentation/technical-articles/Synchronizing-Sample-Clocks-of-a-Data-Converter-Array-Web.pdf
In our system we will have a set of separate rack-mount boxes (one HMC7044 on a separate PCB per box) connected with “long” coax cables. All boxes shall be using identical design. Expected distances between the HMC7044s including board traces can be 1,64 - 3,28 ft. I’m afraid that we will hit limitation of maximum possible delay in HMC7044 for achieving synchronized CLK/SCLK output across the system . We want to feed ADCs with 122.88 MHz so with Fvco=2949.12MHz we can have maximum 3ns delay with integrated digital/analog delay blocks - please correct me if I’m wrong but I think that multislip digital delay elements can´t be used in this case.
In case of just one slave box I think it can be ok but with more slaves connected in cascade we will have to use additional external delay buffers (with problems like phase noise degradation, jitter and stuff) or use star topology with SYNC fanout.
Also, I’d like to double check that I understand correctly the principle/sequence of synchronization of multiple HMC and their ADCs. My understanding is that I need to:
- Configure all HMC7044s for CLKOUTs synchronization:
- Set all output delay elements (in CLKOUTs branches) in all HMC7044s properly such that outputs from all HMC7044s will be aligned in time/phase
- SYNC/RFSYNCIN are configured for multichip synchronization
- Once all is ready to run apply SYNC pulse from the FPGA to the master HMC7044. This event propagates through SCLKOUTs and RFSYNCINs to all slave HMC7044s
- Configure all ADCs (JESD slaves) and let them wait for SYSREF pulse
- Set output delay elements in SCLKOUTs branches appropriately
- SYNC/RFSYNCIN are configured for pulse generator mode
- Again apply SYNC pulse from the FPGA to the master which will cause synchronized SYSREF pulses on all ADcs across the system
Also...is there an application note about board-to-board crossing (chip > diff out > SE coaxial cable...)? We would like to use single-ended connection between boards instead of two coaxial cables for one differential signal.
Thanks and regards,