We are interested in AD9691 multichip synchronization, with different decimation rates being used in different channels, either within the same chip or between chips. The JESD204B link guarantees deterministic latency across the link, but does not consider latency in the adc front end core.
It is understood that the JESD Link, input clock dividers and downconverter NCOs can be synchronized. However, does the chip provide deterministic latency from sample capture time to the time a sample is input into the JESD204B link? Is this true for the scenario described (channels across multiple chips running at different decimation rates)?
The datasheet does not seem to address the timing of the ADC front end core. Figure 4 shows an example timing sequence for one particular set of options (L=8,M=2,F=1) but with no text description and no description of timing for other options.