A customer is observing subharmonics issue by EVAL-HMC7043. Data, setting and register file is in the attachment. What is wrong with register setting? Please provide some advice.
There is not any significant error in the register settings. SYSREF Timer causes those spurs when enabled as mentioned in your document. These spurs can be eliminated systematically by disabling SYSREF Timer or disabling RFSYNC input buffer depending on the requirements and the system scenario.
Another point in the register settings that needs to be changed is 0x009F and 0x00A0 should be updated as given in Table-40 in the datasheet. This is not related with the spurs but better to use the updated values.
With the customer's test results,SYSREF Timer enabled => Subharmonics are caused with regardless of RFSYNC input buffer enabled or disabled.
Anyway I have a couple of questions.- Is this behavior normal that spurs (subharmonics) are caused by SYSREF Timer enabled, or is this unexpected behavior? - In case that SYSREF Timer is disabled, does HMC7043 work properly as clock fan out buffer for JESD204B?
- Yes, SYSREF Timer internally generate div-by-8 frequency signal and this cause spurs at the output, that is normal.
- That depends on the application and system requirements, but mostly yes, HMC7043 still can be used for JESD204B systems. If SYSREF pulses are only required as an initialization procedure, then SYSREF Timer can be disabled after finishing initialization. This won't affect the output signals and synchronization will still be preserved. Similarly SYSREF Timer is disabled normally and can be enabled dynamically when required in operation.
Understood. Thanks for your explanation.
I will discuss with local FAE for further detail.
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