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SSM2518 codec BCLK used as MCLK

Question asked by ahj40 on May 22, 2017
Latest reply on May 24, 2017 by DaveThib

Dear experts

I feel that I'm digging my self into a deep hole, and hope that someone have some experience with the SSM2518 codec (and I2S)...


We drive the codec from a SSC port, and use the BCLK as MCLK, feeding it to the MCLK pin and connect BCLK pin to ground. Data sheet says that the BCLK can be used as MCLK as long as it is in the range of "internal master clock frequencies (2.048 MHz to 6.144MHz)"


The SSC port divide a peripheral clock of 66MHz. As an example we set the port to generate 16kHz sampled signal, BCLK is set to (66MHz / (2*8)) = 4.125MHz and LRCLK is calculated to BCLK/(2*(128+1)) = 15988 Hz


We really tried many different divider values, and only succeeded once to get some low quality sound at Fs = 8KHz !

Are our frequencies too far off, or do we really have to use a distinct MCLK signal too ?


As frustration grew, we also tried to feed MCLK pin direct with a crystal oscillator of 12.288 MHz (and BCLK to the BCLK pin), this gave us reasonable sound at more sample rates, but the sound is full of "noise". I expect it is due to the fact that the MCLK frequency was "free running" (not synchronously).


Right now we are very close to give up, and try to find a codec that can act as "master" and deliver the magic frequencies to our own SSC port. I hope that someone can help me judge if I'm really have to do that, or there is hope for a solution with the SSM2518.


Bonus info:

We use the SSM2518 in two different prototypes (embedded Linux), and want to generate UI sounds and beeps, voice announcements and background music.