I want to use 3 synchronised units of AD9364 on my design (always on RX mode). All of them:
- will use the same reference frequency (40MHz)
- will work at a 50MHz sampling frequency
- will be synchronised by a common signal sent to H5 (SYNCH_IN), as shown in chapter "BASEBAND SYNCHRONIZATION" on page 83/120 of AD9364 Reference Manual (UG-673)
- will send the RX sampled data to the same FPGA.
My questions, with this configuration...:
- will signals DATA_CLK and RX_FRAME from the 3 AD9364 be absolutely synchronised?
- can I use signals DATA_CLK and RX_FRAME from just one of the AD9364 to provide RX data sampling timing for the whole system (the 3 AD9364 chips).
As you can guess, my intention is to simplify PCB design. I want only to route lines DATA_CLK and RX_FRAME from just one of the AD9364 to the FPGA.