As per my application i need to phase match need to achieve +/- 4 degree between channel to channel.
I selected ad9656 ADC, it have four channels. I nee to match the Phase between two ADCs of AD9656 (i.e 8 CH).
I used the JESD204B PLL,which supports the 7 outputs of CLK and SYSREF.
I connected CLK and SYSREF to ADC and one more clock group of CLK and SYSREF to FPGA.
I did the following things to achieve the phase match between channels to channels as well as ADC to ADC.
1. The Jitter from the PLL is 116.5fs and ADC uncertain jitter 135.5 fs = Total jitter (178fs).
2. To meet the Setup and Hold time , i followed the article MS-2677 and length matched the CLK and SYSREF with in 2 inchs.
3. As per article MS-2677, i found Tvalid window of ADC (ad9656) is = 0.722 ns , The PLL offers the delay adjustment as = 0.32 ns to meet the setup and hold time.
4. Simulated the ADC front end S -parameter with ADS i get the result as +/-1 degree Variation in the Path due to the External Discrete tolerance. (Refer - Attachment for Front End)
5. Aperture delay (ta) of ADC - 1ns , Is it also introduces the phase error between ADC to ADC - If it is how can i rectify that.?