In ADF4106, the phase detector frequency = input reference frequency? or the chip uses its own internal clock frequency?
On behalf of Robert Brennan:The phase detector frequency is derived directly from the reference frequency. There is a R divider on the reference input path. The output of the R divider drives is the phase detector frequency. The R divider can be set to 1, 2, 3, 4… In an integer-N PLL, like the ADF4106, the PFD frequency sets the output frequency resolution.
See the highlighted region of the ADF4106:
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