AnsweredAssumed Answered

Latency problem with AD9915

Question asked by racined on May 19, 2017
Latest reply on May 24, 2017 by racined

Hi,

I am using the AD9915 demonstration board to generate a CW for a precise duration (10ns to .655ms). The goal is to control an Acousto-Optic Modulator (AOM) as advertized on the data sheet.

For this I use the sweep mode with frequency jump enabled and no dwell high. This gives me DC=0, then CW, then DC=0. I am getting some erratic results however for the duration of my CW pulse. This approach was inspired by this thread in engineering zone: https://ez.analog.com/thread/81157.

The general settings are to provide a 10MHz clock from a GPS disciplined oscillator converted to ECL square signal with a Linear Devices LTC6957HMS-1 demonstration board. I use the AD9915 internal PLL to set the clock to 2.4GHz. I enable OSK, enable sin output, direct the DRG to frequency, use profile 0 and use the DRCTL pin to trigger the pulse.

The DRG settings are with the lower limit at 0 and the upper limit at 100MHz (M=0xaaaaaab). I set the rising step size to 1, set the lower jump point to 1 and upper jump point to M-1. I then vary the ramp rate according the pulse duration that I need (P=N=13 gives a 100ns pulse duration). This scheme provides one step size interval at 0Hz and one step size interval at 100MHz. With no dwell high enabled, the DDS returns to 0Hz at the end of those two step size intervals.

The problem that I have is that the latency seems to be erratic and because of that my pulse duration is unpredictable. Both values of the rising and falling ramp rate (P and N) influence the pulse duration (I would have thought that only the rising ramp rate would be important since I am using a positive ramp). For some values of P and N the timing is an integers of 10ns (e.g. 4 gives 40ns, 7: 60ns, 13: 100ns, 19: 140ns) while for other values this is not an integer at all.

Below is the registers dump that shows the problem with N and P set to 12:

<?xml version="1.0" encoding="utf-8"?>
<Settings ExternalClock="10">
<Registers>
<Register Address="00" Data="00010300" />
<Register Address="01" Data="008C6000" />
<Register Address="02" Data="0004787F" />
<Register Address="03" Data="00052120" />
<Register Address="04" Data="00000000" />
<Register Address="05" Data="0AAAAAAB" />
<Register Address="06" Data="00000001" />
<Register Address="07" Data="00000000" />
<Register Address="08" Data="000C000C" />
<Register Address="09" Data="00000002" />
<Register Address="0A" Data="0AAAAAAA" />
<Register Address="0B" Data="0AAAAAAB" />
<Register Address="0C" Data="0FFF0000" />
<Register Address="0D" Data="00000000" />
<Register Address="0E" Data="00000000" />
<Register Address="0F" Data="00000000" />
<Register Address="10" Data="00000000" />
<Register Address="11" Data="00000000" />
<Register Address="12" Data="00000000" />
<Register Address="13" Data="00000000" />
<Register Address="14" Data="00000000" />
<Register Address="15" Data="00000000" />
<Register Address="16" Data="00000000" />
<Register Address="17" Data="00000000" />
<Register Address="18" Data="00000000" />
<Register Address="19" Data="00000000" />
<Register Address="1A" Data="00000000" />
<Register Address="1B" Data="A3000024" />
</Registers>
</Settings>

I attaching a Python script which will simulate the problem. I hope that this timing issue problem can be addressed. The time invested in getting this to work is quite significant. I would be unfortunate to have to discard everything at this point.

Thanks,

Outcomes