I adi_AFE_TiaChanCal(), there is a portion of the code named Step 2, which refers to what the Hardware Reference Manual describes as the ADC Gain error measurement (the HRM calls it Step 3). This is when it runs the sequence named seq_afe_tiachancal2 where the mux is selected to have the ADC measure the difference between VREF and VBIAS. My understanding from reading the documentation is that the ADC channel would have a gain of 1x in this scenario. That is, is it the case that the only time the channel has a gain of 1.5x is when the TIA is being measured?
If so, then I think there's a mistake in adi_AFE_TiaChanCal(), as the calculation for the gain error correction in this step just after running seq_afe_tiachancal2 contains a factor of 1.5.
Can you tell me if the code is correct or incorrect? I'm attaching details.