I know it's a quite frequently asked question. But my situation is slightly different. so I wanna make sure my idea about the implementation is correct. So if anyone could give me a comments, it would be very welcome.
I found that the block axi_ad9361_dac_dma is a fifo, which buffers the IQ data from the PS. The output IQ data will be available in fifo_rd_dout[63:0] once the fifo_rd_en is valid (I suppose it would be high voltage). The buffered IQ data will be read according to the fifo_rd_clk.
In the original design, this fifo_rd_clk comes from axi_ad9361 block, the frequency of which would be tx_samp_freq. Hence, the IQ data will be transmitted in the tx_samp_freq rate. Under this assumption, if we change the fifo_rd_clk to a real low rate data clk generated by the axi_ad9361 clk rather than the tx_samp_freq clk and add an additional HDL modulation block clocked by the tx_samp_freq between util_ad9361_dac_upack and axi_ad9361_dac_dma, the system design would not be modified significantly except the changes mentioned above.
1. Because the source code of axi_ad9361_dac_dma cannot be seen. Does anyone know how does fifo_rd_en perform? According to my understading, it probably performs as the normal fifo does.
2. When is the output of fifo_rd_dout[63:0] available?(the next clock after fifo_rd_en is valid?)
3.Is there any other problem? in this implementation idea?