I'm using an AD-FMCDAQ2-EBZ board (Rev E) connected to a Xilinx Kintex KCU105 dev board. I'm having intermittent pll lock failures with the AD9680. The AD9523-1 is configured per the No-OS example e.g. 1 GHz clock to the 9680 and a 7.8125MHz SYSREF clock. When the AD9680 fails to achieve lock I can verify by probing R55 that there is indeed a 1GHz clock present. So I don't think it is a clock chip configuration issue ( stock config and clock is there ).
I have configured the 9680 slightly differently from the full take settings of the No-OS example. I have two DDC's enabled, chip decimation of 8, and three half band filters. I also have set the FTW and issued a DDC soft reset after doing so. Perhaps there is a particular order the registers need to be set?
The troubling thing is that the pll does lock sometimes, but if it doesn't then it never does. Any clues?