HDL branch: dev
h/w: Zed + fmcomms1
tool: Vivado 2016.4
I'm trying to learning a thing or two about CDC related design considerations and while thus trying to understand the cdc paths in the fmcomms1 reference design.
While investigating CDC report post-implementation I came across the 'critical severity path' documented below with the schematic.
1. I am trying to understand why this path does not need a synchronizer since it's passing from the s_axi_clk to the fifo_rd_clk (dac_div_clk). There are NO timing violations post-implementation so the tool doesn't seem to think there's any problems post implementation. The eot_mem_reg' is clocked by the s_axi_clk while the 'active_reg' is clocked by the fifo_rd_clk.
2. What exactly are the beat counter registers doing?
So armed with all this (2-whole days worth) of CDC knowledge I want to try and understand why one can do away with synchronization in this specific case. It doesn't look like there are any constraints placed on any path in this little subset of crossed logic.
There seems to be comb logic between the last FF in the source domain and the first FF in the destination domain. Isn't this incorrect?. Moreover at the destination there is no syncronizer to sync the Q o/p of the 'eot_mem_reg' to the D i/p of the 'active_reg'. Is this because the eot in non-cyclic mode is asserted only once => slow changing signal => no need for synchronization?
Clearly this is an 'end of transfer flag' from the req_arb submodule being used in the data_mover submodule. And since the design is tried and tested extensively by now by AD folks and I know it works just fine on hardware, I must be misunderstanding something about CDC analysis? Moreover I do not have a very detailed understanding of the dma module and so don't have a good starting point (documenation) to understand all signal paths.
Can you point me in the right direction in trying to analyze these?
Note: There are actually a bunch of other paths in the same axi_ad9122_dma instance and perhaps if I can understand the above mentioned analyses I can apply the same methods to analyze the remaining critical paths.
Again: All timing requirements are met post-implementaiton.
Module: axi_ad9122_dma instance of the ad_dmac IP
|Description||1-bit unknown CDC circuitry|