Hello, AD Engineers.
I am testing ad1937 DAC slave mode and I have some noise issue from ad1937.
Actually I am using independent clock source for DSP and AD1937 MCLKI. I think that different clock source can cause noise, because ad1937 master mode doesn't have any noise and even when I set PLL source to DLRCLK in slave mode, the noise is gone.
Here, I have a question about using internal PLL.
When I set PLL input as DLRCLK, sometimes PLL lock is set to 1 but sometimes lock bit isn't set at all, also there is no audio out from DAC.
Is there some limitation about using internal PLL? For example, PLL input frequency should be 48kHz.
Because I tried to use 44.1kHz for LRCLK, the pll lock bit wasn't set.
Can you please explain to me how to use internal PLL?
One more question is,
Is Bit 2:1 in PLL and Clock Control 0 Register meaningful just for that PLL input is MCLKI/MCLKXI? or does that field determine pll frequency?
To help understand my clock condition, I attached block diagram.
Is it possible for having noise in slave mode?