I have projected and built a simple synthesizer based on the ADF4350, that have to generate a signal on the primary output (OUT1 in the schematic) frequency between 1.5-2.5GHz with a channel spacing of at least 1MHz.
The loop filter is been designed with the ADIsimPLL software.
My problem is that the pll periodically unlock with a frequency of about 33Hz for 250us (this is the Muxout pin set as Digital Lock detect).
The reference frequency is of 25MHZ provided by a crystal oscillator (TCO-710x) with a 3rd harmonic measured of -20dBc. I have tried to insert a chebyshev band pass filter of 3rd order with center frequency of 25MHz and 10MHz bandwidth... not is changed: nothing if i use a signal generator as reference signal.
What can causes this behaviour? Can it be a solder/layout problem or it can be due by an erroneous loop filter?
I have enclosed the schematic, the register settings (well write by a PIC Microcontroller according the initialization sequence) and the ADIsimPLL project file.