My application uses three AD9649s controlled by an Altera Cyclone IV FPGA.
The three devices have separate interfaces to the FPGA for the parallel data buses, and a common SPI controller (with three chip-select outputs) for the configuration interfaces.
Conversion clock is 57.6 MHz, supplied continuously from a crystal oscillator.
SPI SCLK frequency is 14.4 MHz (i.e. 1/4 of conversion clock, divided in FPGA).
Digital and analog supply voltages are both 1.8 V.
The parallel data bus is working on all three devices, but the SPI configuration interface does not respond to commands.
For read operations from any address, during the last 8 SCLK cycles where the AD9649 should be driving read data, SDIO appears to be tri-stated (voltage decays slowly to zero). Write operations (e.g. to register 0x14 to set output data format to 2's complement, followed by write to register 0xFF to latch the data), are ignored - output data format is unchanged.
Attached is a scope plot of the bus signals for an example read operation. There are no signal integrity problems apparent, and the sequence is as per fig 55 in the data sheet.
What am I doing wrong?