How can I enable the second receiver in the hdl design in Vivado? Thanks for your time.
I think you where confused by the notations. For git branch hdl_2016_r2, if parameter DISABLE = 0, means the channel is enabled, fmcomms2 has 2 TX and 2 RX channels, meaning the ad9361 chip and the ad9361_core will be configured in 2R2T mode, for this parameter MODE_1R1T = 0.
If you want more info about this communication modes between AD9361 and the FPGA on fmcomms2, see "AD9361 Reference Manual UG-570". -> DIGITAL INTERFACE SPECIFICATION --> DUAL PORT FULL DUPLEX MODE (LVDS).Anyway both RX channels are enabled in hdl for fmcomms2 for the released branch or earlier.What made you think otherwise? and what git branch are you using?
What evaluation board are you using ?fmcomms2/3/4/5, pzsdr1/2.And are you using Linux or no-Os?
Oh I'm using FMCOMMS2 and no-Os. I can see the second rx input port as a disabled port on the block diagram in vivado, just wondering how to enable it really.
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