I have an ADC driver having a flipped output at idle. Meaning that one output stays high, one stays low and as a pulse is incident they switch polarity and go back to their initial positions.
Ideally, when AD9680 is considered, a signal having 2V(actually 2.05V but just for ease of discussion I use 2V) should be present.
I understand that the ideal signal utilizin maximum range of AD9680-500 would be a differential signal having 2V common mode and a differential swing of 2Vpp.
what would happen if the signal has a higher common mode voltage as follows, 2.25V common mode voltage and 1Vpp swing..
and what would happen if the common mode is further shifted to 2.5V, swing is 1Vpp. In this case, the instantenous voltage level and also idle voltage level is 2.75V which is ADC's amr rating.
In my pulsed applicaiton, differential outputs stay flipped for 99% of the time and they change polarity for 1% of the time. If the common mode is higher, I wonder how would ADC react to this.
thanks in advance