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ADF4107 register sequence

Question asked by das@1059 on May 6, 2017
Latest reply on Dec 5, 2017 by das@1059


 I am using 4107 PLL for generating stable frequency of 6.9 GHz. ADF4107 configure by three method in that i'm using counter reset method follow the sequence as mentioned in the data sheet but  i'm not getting any update in that can you please help me in that and what time should be set between two register and maximum LE time in that  CE pin is contentiously high.


Thank you.