Vanteon is trying to debug their Rx side on the AD9371. They want to confirm first that the JESD interface is working correctly, so they are using the pattern generator on the Rx side to take the RX front end out of the equation. They are having trouble understanding how the data from the pattern generator gets framed in the JESD interface. Their question follows;
In an attempt to remove the RF domain from the equation, I’ve tried resorting to using the AD9371 pattern generator function in the Mykonos API but I am not getting results that I expect. I am setting the pattern to 0x5a5a5 (which is the default in the ADI code) and I get 0x04820482 coming out of the Xilinx JESD PHY on the zc706. I guess I don’t understand what to expect – the API code says the pattern generator is 20 bits. But the ADCs are 16-bit, so I don’t understand how the pattern is handled by the RX framer.
Doesn’t the framer expect to use 16-bit data inputs from the ADCs?
I have a suspicion there is something about how the I/Q data is formatted onto a single lane configuration that we should know about.
There may be some documentation about this somewhere out there, if there is can you point me to it?