For power saving reasons, I want to temporarily shut down VDD and VSS, while VL remains. After return of VDD and VSS, are the switch states still valid? Or are they lost or reset to off state?
For my application i have to program the ADG2128 each time to get the state that i want after each power OFF and ON sequence.
Even the VL pin is for the digital peripherals, the core supply is provided by VSS and VDD, the states becomes reset.
Its from my Firmware engineer's experience.
The golden power-up sequence is:
4. Digital Inputs
5. Analog Inputs.
For your application, it is not recommended to shut down Vdd and Vss while VL is also present. Since power supplies are not present, the blocks inside the device are not powered up properly and could cause unknown switch/es state. What I would recommend is to shut down also the VL pin, if you are aiming for power saving. Then follow the power-up sequence mentioned above every time the device is to be operated.
Let me know if this helps.
Hi May, hi ArunKuttath,
thank you for your helpful answers!
So to avoid loss of switch states, I will split up my supply rails and only shut down some power hungry components, while leaving the ADG2128 supply intact.
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