In my design, AD9826 is configured working in 1-channel SHA mode. When it is configured in the 8 bits mode, it's working correctly. However, the douts become uncorrect in the 16 bits mode.
Most likely the connector error was only on the lower byte of data, where the upper byte was unaffected. It could also be a timing difference with the MUX.
I am moving the thread to the High speed ADC community. Someone here will respond to your inquiry.
Here is the timing diagram for the 1 channel SHA mode:
Are you observing the this timing in your design?
Can you post a bit more clarification on how the outputs are not correct?
Raw data would be useful. Scope shots would also be useful.
Thank you for your reply.
All the timing satisfies the timing diagram in the datasheet. After days of debugging, it seems a connector between the ad9826 and FPGA board is responsible for the unstable Dout. However, I still don't understand why it working fine in the 8 bits mode. Perhaps the 16 bits mode has a higher data rates.
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