AnsweredAssumed Answered

AD9371 Jesd does not sync

Question asked by Reis on Apr 30, 2017
Latest reply on May 4, 2017 by Vinod

Hi,

I m building an application for initializing and configuring AD9371, uising the mykonos api, and the common drivers. 

I followed the procedure described on the headless.c and all initializations seam correct until BBIC JESD Sync Verification.

 

The xcvr cores initialization is made successfully using the setup functions of the common drivers.

The rx Jesd seems synchronized, reading the FPGA registers. But the Rx_Os and the Tx fail synchronization.

Any idea how to solve the problem ?

 

This is my BBIC Inialization code:

 

/*** < Action: Insert BBIC Initialization Code Here > ***/


dev_clk = ((&mykDevice)->clocks->deviceClock_kHz);

rx_lane_rate_kHz = (((&mykDevice)->rx->rxProfile->iqRate_kHz *
(&mykDevice)->rx->framer->M *
20))/ ((&mykDevice)->rx->framer->serializerLanesEnabled);

rx_os_lane_rate_kHz = (((&mykDevice)->obsRx->orxProfile->iqRate_kHz *
(&mykDevice)->obsRx->framer->M *
30))/ ((&mykDevice)->obsRx->framer->serializerLanesEnabled);

tx_lane_rate_kHz = (((&mykDevice)->tx->txProfile->iqRate_kHz *
(&mykDevice)->tx->deframer->M *
20))/ ((&mykDevice)->tx->deframer->deserializerLanesEnabled);

axi_clkgen_disable(&bbic_tx_clk);
axi_clkgen_disable(&bbic_rx_clk);
axi_clkgen_disable(&bbic_rx_os_clk);

if(axi_clkgen_set_rate(&bbic_tx_clk, dev_clk*1000, dev_clk*1000)<0){
xil_printf("TX CLOCK ERROR\n");
}
if(axi_clkgen_set_rate(&bbic_rx_clk, dev_clk*1000, dev_clk*1000)<0){
xil_printf("RX CLOCK ERROR\n");
}
if(axi_clkgen_set_rate(&bbic_rx_os_clk, dev_clk*1000, dev_clk*1000)<0){
xil_printf("RX OS CLOCK ERROR\n");
}

axi_clkgen_enable(&bbic_tx_clk);
axi_clkgen_enable(&bbic_rx_clk);
axi_clkgen_enable(&bbic_rx_os_clk);

adc_setup(bbic_adc);
dac_setup(bbic_dac);

rx_lane_rate_kHz = adxcvr_clk_round_rate(&bbic_rx_xcvr,rx_lane_rate_kHz,dev_clk*1000);

if(adxcvr_clk_set_rate(&bbic_rx_xcvr,rx_lane_rate_kHz,dev_clk*1000)<0){
xil_printf("RX JESD CLK ERROR\n");
}

rx_os_lane_rate_kHz = adxcvr_clk_round_rate(&bbic_rx_os_xcvr,rx_os_lane_rate_kHz,dev_clk*1000);

if(adxcvr_clk_set_rate(&bbic_rx_os_xcvr,rx_os_lane_rate_kHz,dev_clk*1000)<0){
xil_printf("RX OS JESD CLK ERROR\n");
}

tx_lane_rate_kHz = adxcvr_clk_round_rate(&bbic_tx_xcvr,tx_lane_rate_kHz,dev_clk*1000);

if(adxcvr_clk_set_rate(&bbic_tx_xcvr,tx_lane_rate_kHz,dev_clk*1000)<0){
xil_printf("TX JESD CLK ERROR\n");
}

jesd_setup(bbic_rx_jesd);
jesd_setup(bbic_rx_os_jesd);
jesd_setup(bbic_tx_jesd);

 

 

And this is my code for Jesd Sync verification where Rx_os and the Tx fail synchronization.

 

/*************************************************************************/
/***** Enable SYSREF to Mykonos and BBIC *****/
/*************************************************************************/
/*** < Action: Sends SYSREF Here > ***/

AD9528_setupSYSREF(&ad9528Clock,16,CONTINUOUS,EIGHT_PULSES);
AD9528_requestSysref(&ad9528Clock,1);

adxcvr_clk_enable(&bbic_rx_xcvr);
jesd_status(bbic_rx_jesd);

adxcvr_clk_enable(&bbic_rx_os_xcvr);
jesd_status(bbic_rx_os_jesd);

adxcvr_clk_enable(&bbic_tx_xcvr);
jesd_status(bbic_tx_jesd);

AD9528_requestSysref(&ad9528Clock,0);

 

Thank you.

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