I'm designing a precision analog Opto link with a straight forward AD - DA conversion.
As ADC I'm using an LTC2378-20. The SPI- Signals are generated and processed with a CLPD. The final clock burst
and the data sequence are fed to two opto transmitters. On the receiver side tere is also a CPLD for processing
the Clock ans data signals. Ths sync frame and the initialisation sequences are also regenerated with this CPLD.
The system clock frequency is 33Mhz
Now have a problem getting an output signal from the AD5791.
Vcc; VCCio = 3,3V
Vdd=+10V; Vss =-10V
VrefP =5V; Vrefn =5V
!LDAC Pin Connected to Low;
!CLR Pin connected to Vcc via 10K;
!Reset Pin driven by reset generator (see SEQ01 File)
SDO open circuit
DAC Output directly connected to AD8657 as Voltage follower
Signals SDIN; SCLK; SYNC and Reset generated by CPLD as mentioned above
1) Setting !RESET to high (generated by a reset generator)
2) first SPI sequence Reset;NOP: DB0 to DB23 =>0000 0000 0000 0000 0000 0000
This sequence mostly is not complete, because SDIN; SCLK; SYNC are
not synchronuous to the reset
3) second SPI sequence
Setting the software control register: 0100 0000 0000 0000 0000 0101
LDAC=1; CLR=>0; RESET=>1
4) third SPI sequence
Setting the Control register: 0010 0000 0000 0000 0010 0010
RBUF=>1; SDODIS=>1; Write Control register 0010
5) fourth and following sequences D/A Conversion: 0001 xxxx xxxx xxxx xxxx xxxx (x=>Data)
DB20 is continuously set high.
The screen shots of the sequences you can find in the appendix.
Additionnally the tailing and leadinng sync edges are shown in detail
green: !RESET (Power-ON-Reset)
yellow: !SYNC (Sync- Frame)
red: SCLK: (Clock Burst)
blue: SDIN (Data in, DB20 fixed to 1)
6.)The SDO- Signal is also present when setting the SDODIS bit to 0
In the appendix, there is also a screenshot, which covers tis condition.
The SDO- Signal is represented by the green trace
I'm shure, the device is working, because sometines I had the input triangle as distorted Output signal, when I manipulated the Signals applied to the AD5791 with my fingers.
Please answer the following Questions:
What is the correct Initialisation Sequence for straight D/A Conversion
Are the registers set in the right manner?
Is the timing OK
What else can I do getting the DAC to work
JPEGs in the Appendix:
File_01.jpg: Sequence 01: Power-ON-Reset
File_02.jpg: Sequence 02: Write Software Control register
File_03.jpg: Sequence 03: Write Control Register
File_04.jpg: Sequence 04: Continuous DA- Conversion write
File_05.jpg: Sync Frame falling edge Detail
File_06.jpg: Sync Frame rising edge Detail
File_07.jpg: SDO Output (with SODIS=> low)
File_08.jpg: SDO Output 2 Sequences
Many thanks in advance