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ADIS16375 data valid timing

Question asked by Huangfeihong on Apr 26, 2017
Latest reply on Apr 26, 2017 by NevadaMark

Hi everyone,

    I'm a little confused with the data valid timing of ADIS16375 . The timing diagram in figure 4 of the data sheet just as below:

    t2 in the figure seems like the time between SYNC clock's rising edge and the data invalid, but in table 2, t2 has been explained as the time between sync clock and data-ready output. The figure and the table present me a contradictory explaintion.

   Anyone can tell me when should i begin to read the register? After the rising edge of data ready signal or the falling edge? 
Thanks a lot!