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Question asked by FreedomSabre on Apr 26, 2017
Latest reply on May 3, 2017 by MRichardson

I use HMC698 PLL chip and an HMC509 VCO , PFD frequency is 100MHz,  op amp is THS4031ID or AD797,but can't lock either


in HMC698  datasheet,PFD INVERT function   CMOS compatible input control bit Logic “LOW” = NORMAL Logic “HIGH” = INVERT,what does this mean,i use the circuit as below,in this way ,the INV should be connected to LOW or to high?


in the datasheet ,the loop filter is only 2 order ,but i use the Hittite design software,the loop filter is always 3 order,what's  the difference,how can i calculate a 2 order loop filter