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ADAU1761 MCLK and POR sequence question

Question asked by Sam.S on Apr 25, 2017
Latest reply on May 3, 2017 by Sam.S

Dear Sir,

 

Good day!!

 

Our customer have question about the ADAU1761 POR sequence and MCLK : 

 

Their met an issue, due to their system design, MCLK was provided by external device.

If the MCLK clock into the ADAU1761 first than VDD3V3, their product have big noise emit out after power on sometimes. They want to add a buffer to control MCLK input clock to fixed this issue.

 

 Our customer RD want to verified that below power sequence is correct:

 

1. Initial state: AVDD/MCLK is off
2. Given AVDD to DSP, let DVDDOUT have 1.5V reference voltage
3. Delay > 14ms
4. Give MCLK to DSP
5. Check if PLL is lock
6. Start SigmalStudio initialize sequence (Enable the Core clock, Load the register setting)

 

So, above the procedure is correct, or any step should be modified?

 

BTW, the DVDDOUT should be must from low to high when power on, and then pull low again to let POR active for reset more completely(?) like below sequence?

Or AVDD just one time get high until device shut down?

 

 

ADAU1761 POR sequence

 

Looking forward your any advised.

Thank you very much!!

 

Sam

 

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