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Explain Tx tuning

Question asked by ENGINEER on Apr 24, 2017
Latest reply on Apr 25, 2017 by mhennerich

Hi,

   Custom AD9361 board

                         1. petalinux with iio driver ported.

                         2. Tx spectrum is with skirt.

                         3. trying to understand it more, led more to few doubts on Tx tuning.

 

===================

4.022162] Btrfs loaded
[ 4.207007] SAMPL CLK: 25000000 tuning: RX
[ 4.211027] 0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
[ 4.215443] 0:o # # # # # o o o o o o o o o o
[ 4.219870] 1:o o o o o o o o o o o o o o o o
[ 4.224297]
[ 4.366686] SAMPL CLK: 40000000 tuning: RX
[ 4.370704] 0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
[ 4.375121] 0:o # # # # # # o o o o o o o o #
[ 4.379547] 1:o o o o o o o o # # # # # # o o
[ 4.383974]
[ 4.557706] SAMPL CLK: 61440000 tuning: RX
[ 4.561723] 0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
[ 4.566141] 0:o # # # # # # o o o # # # # # #
[ 4.570568] 1:o o o # # # # # # # # # # # # #
[ 4.574995]
[ 4.576500] SAMPL CLK: 61440000 tuning: RX
[ 4.580560] 0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
[ 4.584977] 0:o # # # # # # o o o # # # # # #
[ 4.589404] 1:o o o # # # # # # # # # # # # #
[ 4.593830]
[ 4.767647] SAMPL CLK: 25000000 tuning: TX
[ 4.771667] 0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
[ 4.776084] 0:# # # # # # # # # # # # # # # #
[ 4.780511] 1:# # o o o o o o o o o o o o o o
[ 4.784938]
[ 4.927353] SAMPL CLK: 40000000 tuning: TX
[ 4.931371] 0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
[ 4.935788] 0:# # # # # # # # # # # # # # # #
[ 4.940215] 1:# # o o o o o o o o o o # # # #
[ 4.944641]
[ 5.118369] SAMPL CLK: 61440000 tuning: TX
[ 5.122392] 0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
[ 5.126809] 0:# # # # # # # # # # # # # # # #
[ 5.131235] 1:# # o o # # # # # # # # # # # #
[ 5.135662]
[ 5.137169] SAMPL CLK: 61440000 tuning: TX
[ 5.141226] 0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
[ 5.145644] 0:# # # # # # # # # # # # # # # #
[ 5.150071] 1:# # o o # # # # # # # # # # # #

=========================

 

questions

1. Is first row related to data clock delay and second one related to data delay ? or is it related to channels?

2. in the driver code, i see that tuning is run for all 16*16=256 combinations of Rx, but only 16 combinations of Tx ?

3. so in below print, there is Tx clk delay CAN be anything but data delay can be only 2 and 3 [o] ?

 

[ 5.145644] 0:# # # # # # # # # # # # # # # #
[ 5.150071] 1:# # o o # # # # # # # # # # # #

 

Thanks

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